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Chips with PCIe 6.0 can already be designed: Synopsys has presented a complete solution
twenty.03.2021 [10:49],
Konstantin Khodakovsky

Until the release of the final specifications PCI Express 6.0 is a few months away, but the final rough draft, released about 5 months ago, allows chip designers and other companies to start introducing cutting-edge technology into their products: no new features will be added or changed. Synopsys, for example, has already unveiled the industry’s first complete PCIe 6 IP solution.0, which allows chip designers to integrate an advanced interface into their 5nm chips.

Synopsys DesignWare IP for PCIe 6.0 includes controller (with Synopsys interface or optional ARM AMBA 5/4/3 AXI interfaces), physical interface (PHY), and Verification blocks. The solution provided by Synopsys allows chip designers to add a controller and physical interface to their 5nm design, and then verify that everything is working correctly.

Developers of ASICs for AI and HPC, GPUs, SSD controllers and other products that are sensitive to bandwidth and take advantage of the bandwidth that PCIe 6 interface can provide are interested in the latest interface.0. We are talking about speeds up to 128 GB / s via x16 interface in each direction. This means that, in theory, a PCIe 6 capable device.0 can exchange 256GB of data per second.

PCIe 6 controller.0 from Synopsys in full compliance with the standard increases the data transfer rate to 64 gigatransactions per second versus 32 GT / s for PCIe 5.0 and 16 GT / s — for PCIe 4.0. The signal structure of the interface uses a pulse-amplitude modulation (PAM4) transmission scheme instead of a no-return-to-zero (NRZ) pulse train transmission. Signal gradation with four levels will be used for transmission, which will increase the data transmission density and channel capacity. That being said, Synopsys claims to use an optimized data link to deliver ultra-low latency.

Other PCIe 6 features are also supported.0 features like Forward Error Correction with Low Latency (FEC), FLIT mode and L0p low power mode are all key innovations in PCIe 6.0. On top of that, the Synopsys DesignWare PCIe 6 controller.0 also supports proprietary adaptive DSP algorithms that optimize analog and digital stabilization to reduce power consumption by 20% on the interfaces between chips, riser and motherboard.

In the past 1.5 years, M.2 got PCIe 4 support.0. It will take some time before PCIe 5 support appears.0 in leading edge products, but it’s nice to know that PCI-SIG has almost completed the development of the next version of the interface. Today in PCIe 6.0 hardly makes sense in the consumer market, but bandwidth is never too much in data centers. However, years later, PCIe 6.0 will probably reach regular users too.

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