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Russia will create a processor for space for 400 million rubles
26.10.2021 [20:25],
Vladimir Fetisov

It became known that the STC «Module» received 400 million rubles for the creation and launch of the production of chips intended for use in spacecraft of a new generation. Nobody applied for the thematic tender of the Ministry of Industry and Trade except for STC Module, therefore the initial price of the lot was not reduced.

According to CNews, the scientific and technical center «Module» will develop and master the serial production of the control processor of onboard computers for domestic space satellites of a new generation with elements of artificial intelligence. The project is being implemented within the framework of the tender of the Ministry of Industry and Trade with an initial maximum price of 400 million rubles.

Since the application for participation in the tender was submitted only by STC «Module», the tender was declared invalid, but the procurement legislation allowed the ministry to conclude a contract with the only bidder. The terms of reference for the future product says that it must have two interfaces for data exchange with neuroprocessors of the NeuroMatrix architecture, which was developed by the STC «Module». Within the framework of the established agreements, the work will take place until November 30, 2022. In accordance with the contract, this year STC «Module» will receive 100 million rubles, in 2021 — 165 million rubles, and in 2022 — 135 million rubles.

The terms of reference states that in the process of developing a microcircuit, components and materials of domestic production should be used. However, it is allowed to use foreign-made components and construction materials in technically justified cases. Such cases must be justified at the development stage and agreed in the order established by the customer.

As for the product itself, in addition to the already mentioned interfaces of compatibility with chips of the NeuroMatrix architecture, it should include a processor core with a superscalar architecture and a RISC core for controlling built-in interface controllers. Superscalarity implies the simultaneous use of several parallel processes, while the RISC concept is typical for processors with a reduced instruction set.

As for other requirements for the characteristics of the microcircuit, it must receive an interface for connecting external memory, boot ROM, internal static RAM, a hardware regeneration unit for internal static RAM, interrupt and direct memory access controllers, as well as UART, SpaceWire, Ethernet interfaces, SPI, GPIO, JTAG and MKIO. The microcircuit must be made in a cermet case, and its price will become known after the manufacture of an experimental batch.

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