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Intel will create the most secure 10nm structural ASICs for the US military
Intel and the US Department of Defense Advanced Research Projects Agency (DARPA) announced a three-year partnership to develop US platforms for special purpose structural integrated circuits (ASICs) under the Structured Array Hardware for Automatically Realized Applications (SAHARA) Partnership Program. The goal is to create the most advanced chips that the government has complete confidence in.
The military will be confident in the absence of external bugs, and at the same time the United States will support a key domestic chip manufacturer. Structural ASICs are a cross between relatively expensive FPGAs and conventional specialized ASIC accelerators — they allow on the one hand to reduce the cost, and on the other — the time to market.
“We’re combining our most advanced structural ASIC technology from Intel’s eASIC division with state-of-the-art data interface chips and enhanced security protections, all built in the US from start to finish. This will enable developers of defense and commercial electronics to quickly build and deploy their own chips based on Intel’s advanced 10nm semiconductor process, ”said José Roberto Alvarez, CTO, Intel Programmable Solutions.
“Structural ASICs have advantages over FPGAs, which are widely used in many DOD applications. DARPA is partnering with Intel to transform existing and future SAHARA solutions into structured ASICs with significantly higher performance and lower power consumption, said DARPA spokesman Serge Leef. — SAHARA will greatly simplify the ASIC design process through automation, while adding unique security features to support the production of final crystals for tasks requiring zero confidence. In addition, Intel will create in-house manufacturing facilities for structured ASICs based on its 10nm process. «.
SAHARA will feature the University of Florida, Texas A&M University and the University of Maryland to work with Intel to develop countermeasure technologies that will improve the protection of data and intellectual property from reverse engineering and counterfeiting. University teams will use rigorous validation, validation and new attack strategies to ensure the security of the chips. Hardware protection technologies will be integrated into the structural ASIC design process.
Intel will manufacture these chips using its 10nm process technology, and thanks to an improved communication bus, it will be possible to combine multiple heterogeneous crystals under one package.