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TSMC will double production of 5nm chips this year
03.03.2021 [16:34],
Konstantin Khodakovsky

TSMC previously announced plans to increase its capital expenditures to $ 25-28 billion in 2021, with many industry observers attributed this to the development of 3nm capacities in preparation for the production of processors for Intel and other large customers. But according to the forecast of China Renaissance Securities, this is not entirely true.

Currently, TSMC’s 5nm power (N5) allows the production of 55-60 thousand silicon wafers per month. Given the fact that TSMC can no longer service Huawei HiSilicon orders, the main and largest customer for N5 chips is Apple, which uses this technology to produce its latest A14 Bionic and M1 SoCs. Apple is one of the key customers of TSMC, which has early access to the latest technological processes and is one of the first to use the latest nodes.

Later this year, other TSMC customers such as AMD and Qualcomm are predicted to start using the N5, and that’s when the demand for the technology will skyrocket. In an effort to meet the demand for its 5nm norms in 2021 and beyond, TSMC will spend the lion’s share of its capex on expanding N5 capacity, according to analysts.

China Renaissance experts believe that TSMC will double its N5 capacity to 110-120 thousand wafers per month. In other words, by the end of the year, TSMC will have a huge factory specializing exclusively in 5nm technical processes, which currently include N5, N5P and N4. All these processes will be used for many years.

Another technical process designed for many years of work will be N3 (3 nm). Compared to N5, the N3 process is expected to provide up to 15% better performance (for the same power consumption and transistor count) or 30% less power consumption (for the same frequency and transistor count), as well as a 20% increase in SRAM density. and 70% — the density of logic. TSMC expects N3 test production to begin this year and mass production in the second half of 2022. TSMC says interest in 3nm process technology is higher than interest in 5nm and 7nm at the same development stage (i.e. five to six quarters before the official launch). This year the company will build a pilot line N3 with a capacity of about 10-15 thousand plates per month.

3- and 5-nm process codes exclusively use extreme ultraviolet (EUV) lithography. TSMC will need to purchase multiple ASML Twinscan NXE scanners to expand the N5 capacity and equip the N3 plant. EUV instruments take about six months to calibrate, so TSMC’s expansion plans must be very precise so that the equipment is ready when it is needed.

The main uncertainty for TSMC (and to a large extent for the semiconductor industry in general) today is Intel’s plans to print chips on the side. Intel spoke about the intention to transfer orders for the production of some graphics accelerators and single-chip systems to TSMC — it is believed that we are talking about 5- or 7-nm standards. However, it is unclear if Intel intends to transfer production of its high-performance CPUs to TSMC.

In terms of transistor density, Intel’s 10nm process (~ 100 MT / mm2) is comparable to TSMC N7 + technology (~ 115 MT / mm2), but Intel’s own standards may be more convenient for the company, since its processors have been adapted for this production. Meanwhile, TSMC’s 5nm process technology has a significant advantage in terms of transistor density (~ 170 MT / mm2) — it’s hard to ignore, especially when it comes to GPUs. 7nm Intel norms will be ready only in 2023, but even then they will lag behind TSMC N5. Therefore, it will make sense for Intel to outsource some of its products to TSMC.

While it makes financial sense for Intel to use TSMC’s manufacturing facilities to build its products and save on capital investment while focusing on architectural innovation, this may not be the best plan in the long term. If Intel does not catch up with TSMC now, it may lag behind forever. Taiwanese manufacturer already has more experience in EUV lithography. In addition, the company is already starting to set standards in the EUV ecosystem.

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